季明華，博士，1951年生，1982年畢業(yè)于美國加州大學(xué)伯克萊分校學(xué)校電機(jī)工程專業(yè)，獲得工學(xué)博士學(xué)位。
主要經(jīng)歷：
2006.3-2010.10 中芯國際 資深副總裁
2010.10-2015.11 美國格芯（Globalfoundries) 院士/技術(shù)總監(jiān)
2015.11-2018.6 中芯國際 資深副總裁
2018.6-至今 芯恩（青島）集成電路公司 資深副總裁
Books： Total 3
1.Y. Wang, Y. Cheng, and M. Chi; “Green Micro/Nano Electronics”, Science Press, Beijing, 2013.
2. R.Chang, et. al., “Nano-IC Manufacturing Technology“,Chap 3 （CMOS logic and Memory process flow）, 清華大學(xué)出版社,1st Ed, (2014); 2nd Ed (2017).
3. Y. Wang, et.al. ”集成電路工業(yè)全書”，Chap-6, 2nd Ed. Sept, 2018.
4. Y.Wang, et.al. “Handbook of Integrated Circuit Industry”, Chapter 6, to be published, April, 2020.
Publications：Total 101
Some recent 3 yrs (2016-)
1.M.Chi, D.Xiao, and R.Chang, “Fast Development of IC technology in AI and IoT era”, paper #S37-2, ICSICT, 2018; and Symp-1, #5, CSTIC, 2019.
2.M.Chi and H.Wu, “Advanced logic and specialty technologies for VLSI manufacturing in fast expansion at China”, paper #I-4, CSTIC, March 2017.
3.“W.Peng, M.Chi, et.al., “Reduction of “dark-gate” defects in replacement-metal-gate process and middle-of-line contacts for advanced planar CMOS and FinFET technology”, ASMC, paper#8.1, May. 2016.
4.W.Peng, M.Chi, et.al., “Elimination of Tungsten-voids in middle-of-line contacts for advanced planar CMOS and FinFET technology”, ASMC, session#5: poster, May. 2016.
US PATENTS (granted): Total 247
Some recent US patents (2019)：
1.US# 10,290,654: “ Circuit structures with vertically spaced transistors and fabrication methods”, by H.Zang, M.Eller, and M.Chi, May 14, 2019.
2.US# 10,290,634: “Multiple threshold voltages using fin pitch and profile”, by W.Peng, and M.Chi, May 14, 2019.
3.US#10,276,390: “Method and apparatus for reducing threshold voltage mismatch in an integrated circuit”, by M.Chi, M.Zhao, and K.Kikuta, April 30, 2019.
4.US#10,269,811: “Selective SAC capping on fin field effect transistor structures and related methods”, by M.Chi and H.Zang, April 23, 2019.
5.US#10,243,059: “Source/Drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins”, by S.Samavedan, M.Eller, M.Chi, H.Zang; March 26, 2019.
6.US#10,204,991: “Transistor structures and fabrication methods thereof”, by X.Wu, J.Liu, M.Chi, Feb 12, 2019.
7.US#10,177,157: “Transistor structure having multiple n-type and/or p-type elongated regions intersecting under common gate”, by H.Zabg, M.Chi, Jan 8, 2019.
8.US#10,170,377: “Memory cell with recessed source/drain contacts to reduce capacitance”, bu H.Zang and M.Chi, Jan. 1, 2019.
9.US#10,170,353: “Devices and methods for dynamically tunable biasing to backplates and wells”, by H.Zang, and M.Chi, Jan.1, 2019.
10.US#10,170,315: “Semiconductor device having local buried oxide”, by Y.Liu and M.Chi, Jan. 1, 2019.
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